In semiconductor structures wherein a capacitor is used as a storage element, such as seen in Dynamic Random Access Memory (DRAM) devices, it is necessary to connect the access transistor active area to the capacitor bottom plate (storage plate). This connection is known as a buried contact, i.e., other layers or elements are above the contact surface. Typically, buried contacts are no smaller than the lithographic minimum associated with patterning the wafer.
In order to reduce the cost and increase the speed of operation, memory devices have become increasingly more miniaturized. To that end, each individual component of the semiconductor structure must occupy less space on the device. However, because the capacitance of a capacitor is proportional to the area of the electrodes, to operate efficiently, the overall size of the capacitor must be maintained or a new type of improved capacitor must be employed. Notwithstanding the fact that various new types of capacitors have been recently introduced (e.g., trench and stacked capacitors) limitations in the possible level of capacitor miniaturization necessitates modifying other surrounding structures, such as contact surfaces and buried contact areas, in order to decrease the overall size of the semiconductor device.
With the aforementioned shortcomings in mind, it would be advantageous to provide a method of reducing the size of a semiconductor device (or substructures therein) by forming a sublithographic buried contact which: reduces the cell area; improves the capacitor storage plate registration alignment; provides a smaller buried contact area that intercepts alpha particles such that soft error rate is improved; improves the subthreshold voltage characteristics by moving the buried contact edge away from the access transistor; and facilitates formation of a contact that is self-aligned in both directions so that a single, large, rectangular mask can be used to etch a plurality of buried contacts.